Lateral junction type field effect transistor

ABSTRACT

A lateral JFET has a basic structure including an n-type semiconductor layer ( 3 ) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer ( 3 ). Moreover, in the p-type semiconductor layer, there are provided a p + -type gate region layer ( 7 ) extending into the n-type semiconductor layer ( 3 ) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer ( 3 ) and an n + -type drain region layer ( 9 ) spaced from the p + -type gate region layer ( 7 ) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer ( 3 ). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

TECHNICAL FIELD

[0001] The present invention relates to lateral junction field-effecttransistors, and particularly to a lateral junction field-effecttransistor having an ON resistance which can be decreased whilemaintaining a satisfactory breakdown voltage performance.

BACKGROUND ART

[0002] A junction field-effect transistor (hereinafter referred to asJFET) has a pn junction provided on either side of a channel regionwhere carriers are passed therethrough, and a reverse bias voltage isapplied from a gate electrode to extend a depletion layer from the pnjunction into the channel region to control the conductance of thechannel region and carry out such an operation as switching. Inparticular, a lateral JFET refers to the one having a channel regionthrough which carriers move in parallel with the surface of the device.

[0003] The carriers in the channel may be electrons (n-type) or holes(p-type). A JFET having a semiconductor substrate of SiC usually has achannel region which is an n-type impurity region. For convenience ofthe following description, therefore, it is supposed that carriers inthe channel are electrons and accordingly the channel region is ann-type impurity region, however, it should be understood that thechannel region may be a p-type impurity region.

[0004]FIG. 7 shows a cross section of a conventional lateral JFET (U.S.Pat. No. 5,264,713 entitled “Junction Field-Effect Transistor Formed inSilicon Carbide”). On a p-type SiC substrate 110, a p⁺-type epitaxiallayer 112 is provided on which an n⁻-type channel layer 114 is formed.On channel layer 114, an n-type source region 116 and an n-type drainregion 118 are provided on respective sides of a trench 124 locatedtherebetween, and a source electrode 120 and a drain electrode 122 areprovided respectively on the source region and the drain region. On theback surface of SiC substrate 110, a gate contact layer 130 is formed onwhich a gate electrode (not shown) is provided. Trench 124 is providedwith its depth extending through source/drain regions 116 and 118 toenter channel layer 114. Between the bottom of trench 124 and epitaxiallayer 112 of a first conductivity type, a channel is formed in epitaxiallayer 114 of a second conductivity type.

[0005] The concentration of p-type impurities in epitaxial layer 112 ishigher than the concentration of the n-type in epitaxial layer 114 whichincludes the channel, and thus a reverse bias voltage applied to thejunction extends a depletion layer toward the channel. The depletionlayer then occupies the channel to prevent current from passing throughthe channel and accordingly cause an OFF state. Control is thus possibleto cause or not to cause the channel region to be occupied by thedepletion layer by adjusting the magnitude of the reverse bias current.Then, ON/OFF control of current is possible by adjusting the reversebias voltage between, for example, the gate and source.

[0006] For ON/OFF control of a large current, it is highly desirable toreduce an ON resistance in order to decrease the power consumption, forexample. If the ON resistance is reduced by increasing the thickness ofthe channel or the impurity concentration of the channel layer, however,a problem of deterioration in breakdown voltage performance occurs.

[0007]FIG. 8 shows the channel, source, drain and gate for illustratinga breakdown voltage performance of the lateral JFET. FIG. 9 illustratesan electric field distribution between the drain and gate at a breakdownvoltage. The electric field distribution shown in FIG. 9 refers to anelectric field distribution in the n-type epitaxial layer that extendsfrom the p-type epitaxial layer to the drain electrode. Emax in FIG. 9represents a breakdown electric field when the depletion layer has adistance W from the drain to the pn junction. Emax may be represented byexpression (1) below, where q represents an elementary charge, Ndrepresents an n-type impurity concentration in the region from the drainelectrode to the pn junction, and εs represents a dielectric constant ofthe semiconductor.

Emax=qNdW/εs   (1)

[0008] With the source grounded, the drain-gate voltage is at itsmaximum when breakdown occurs. Accordingly, a breakdown voltage Vb,i.e., withstand voltage is represented by following expressions (2)-(4),where Vdgmax represents the maximum voltage applicable to the regionbetween the drain and the gate, and Vgs represents a gate-source voltagenecessary for causing an OFF state.

Vb=Vdgmax−Vgs   (2)

Vdgmax=qNdW2/(2εs)   (3)

Vgs=qNdh2/(2εs)   (4)

[0009] There are two direct methods as described below for reducing theON resistance. For the two methods each, it will be considered whetheror not the breakdown voltage performance is enhanced, namely whether ornot Vb increases.

[0010] (a) The channel thickness h is increased (without changing theimpurity concentration).

[0011] Vgs increases as seen from expression (4) and accordingly Vbdecreases as determined by expression (2), which means that thebreakdown voltage performance is deteriorated.

[0012] (b) The n-type impurity concentration Nd in the n-type epitaxiallayer including the channel is increased. (Vgs is unchanged. In otherwords, the n-type impurity concentration is increased while the channelthickness h is decreased.)

[0013] The n-type impurity concentration in the n-type epitaxial layeris changed to increase Emax as seen from expression (1), while W isdecreased which is known from an expression (which is not shown above).Although a relation between withstand voltage Vdgmax and the n-typeimpurity concentration cannot be derived directly from the expressionsdescribed above, the relation may be determined as shown in FIG. 10. Itis seen from FIG. 10 that withstand voltage Vdgmax decreases as theimpurity concentration increases.

[0014] It is understood from the foregoing discussion that the directdecrease of the ON resistance of the lateral JFET degrades the breakdownvoltage performance thereof.

DISCLOSURE OF THE INVENTION

[0015] One object of the present invention is to provide a lateral JFETstructured to have an ON resistance which can be decreased while a highbreakdown voltage performance thereof is maintained.

[0016] According to one aspect of the present invention, a lateral JFETincludes a first semiconductor layer placed on a semiconductor substrateand containing impurities of a first conductivity type, a secondsemiconductor layer placed on the first semiconductor layer andcontaining impurities of a second conductivity type with a higherimpurity concentration than that of the first semiconductor layer, athird semiconductor layer placed on the second semiconductor layer andcontaining impurities of the first conductivity type, source/drainregion layers spaced from each other by a predetermined distance in thethird semiconductor layer and containing impurities of the secondconductivity type with a higher impurity concentration than that of thesecond semiconductor layer, and a gate region layer provided between thesource/drain region layers in the third semiconductor layer, having itsbottom surface extending into the second semiconductor layer andcontaining impurities of the first conductivity type with a higherimpurity concentration than that of the second semiconductor layer.

[0017] The above-described structure is employed to achieve an electricfield distribution which is a constant electric field similar to that ofparallel-plate capacitors, instead of the electric field distribution ofthe normal junction (pn junction) between impurities of a firstconductivity type and impurities of a second conductivity type. Adecreased ON resistance is thus achieved with a breakdown voltageperformance maintained, as compared with the lateral JFET of theconventional structure.

[0018] Preferably, according to the present invention, the secondsemiconductor layer and the third semiconductor layer have substantiallythe same impurity concentration. With this structure, the ON resistanceis effectively decreased by the greatest degree with the withstandvoltage maintained.

[0019] According to another aspect of the present invention, a lateralJFET includes a first semiconductor layer placed on a semiconductorsubstrate and containing impurities of a first conductivity type, asecond semiconductor layer placed on the first semiconductor layer andcontaining impurities of a second conductivity type with a higherimpurity concentration than that of the first semiconductor layer,source/drain region layers spaced from each other by a predetermineddistance in the second semiconductor layer and containing impurities ofthe second conductivity type with a higher impurity concentration thanthat of the second semiconductor layer, and a gate region layer providedbetween the source/drain region layers in the second semiconductor layerand containing impurities of the first conductivity type with a higherimpurity concentration than that of the second semiconductor layer.

[0020] The above-described structure is employed to achieve an electricfield distribution which is a constant electric field similar to that ofparallel-plate capacitors, instead of the electric field distribution ofthe normal junction (pn junction) between impurities of a firstconductivity type and impurities of a second conductivity type. Adecreased ON resistance is thus achieved with a breakdown voltageperformance maintained, as compared with the lateral JFET of theconventional structure.

[0021] Preferably, according to the present invention, the distancebetween the top of the first semiconductor layer and the bottom of thegate region layer is smaller than the distance of a depletion layerextended by a built-in potential at junction between the secondsemiconductor layer and the gate region layer. With this structure,normally-off is achieved.

[0022] Preferably, according to the present invention, an impurityinjection region is provided in the second semiconductor layer betweenthe first semiconductor layer and the gate region layer, the impurityinjection region having substantially the same impurity concentrationand the same potential as those of the gate region layer. With thisstructure, the channel resistance is further decreased more effectively.Moreover, the ON resistance is further decreased.

[0023] Preferably, according to the present invention, one impurityinjection region as described above is provided. With this structure,the effective channel thickness is increased and thus ON resistance ismore effectively decreased.

[0024] Preferably, according to the present invention, the distancebetween the top of the impurity injection region and the bottom of thegate region layer is smaller than twice the distance of a depletionlayer extended by a built-in potential at junction between the secondsemiconductor layer and the gate region layer, and the distance betweenthe bottom of the impurity injection region and the top of the firstsemiconductor layer is smaller than the distance of a depletion layerextended by a built-in potential at junction between the secondsemiconductor layer and the impurity injection region. With thisstructure, normally-off is achieved.

[0025] Preferably, according to the present invention, at least twoimpurity injection regions as described above are provided. With thisstructure, the channel resistance is further decreased more effectively.Moreover, the ON resistance is further decreased.

[0026] Preferably, according to the present invention, the distancebetween the top of one of the impurity injection regions that is closestto the gate region layer among the impurity injection regions and thebottom of the gate region layer is smaller than twice the distance of adepletion layer extended by a built-in potential at junction between thesecond semiconductor layer and the gate region layer, the distancebetween the impurity injection regions is smaller than twice thedistance of the depletion layer extended by the built-in potential atjunction between the second semiconductor layer and the gate regionlayer, and the distance between the bottom of one of the impurityinjection regions that is closest to the first semiconductor layer amongthe impurity injection regions and the top of the first semiconductorlayer is smaller than the distance of a depletion layer extended by abuilt-in potential at junction between the second semiconductor layerand the impurity injection region. With this structure, normally-off isachieved.

[0027] According to a further aspect of the present invention, a lateralJFET includes a first semiconductor layer placed on a semiconductorsubstrate and containing impurities of a first conductivity type, asecond semiconductor layer placed on the first semiconductor layer andcontaining impurities of a second conductivity type-with a higherimpurity concentration than that of the first semiconductor layer, athird semiconductor layer placed on the second semiconductor layer andcontaining impurities of the first conductivity type, source/drainregion layers spaced from each other by a predetermined distance in thethird semiconductor layer and containing impurities of the secondconductivity type with a higher impurity concentration than that of thesecond semiconductor layer, and a gate region layer provided between thesource/drain region layers in the third semiconductor layer, including aregion having its bottom surface extending into the first semiconductorlayer and a region having its bottom surface extending into the secondsemiconductor layer, and containing impurities of the first conductivitytype with a higher impurity concentration than that of the secondsemiconductor layer.

[0028] Preferably, according to the present invention, the secondsemiconductor layer and the third semiconductor layer have substantiallythe same thickness, and the third semiconductor layer has its impurityconcentration substantially half that of the second semiconductor layer.

[0029] Preferably, according to the present invention, the thirdsemiconductor layer has its thickness substantially half that of thesecond semiconductor layer, and the third semiconductor layer and thesecond semiconductor layer have substantially the same impurityconcentration.

[0030] With this structure, the third semiconductor layer locatedbetween the gate region layer and the drain region layer as well as apart of the second semiconductor layer that is in contact with the thirdsemiconductor layer all are changed into a depletion layer when apredetermined voltage is applied. Accordingly, the lateral JFET having ahigh withstand voltage is easily achieved without increase in thicknessof the second semiconductor layer and increase in resistance.

[0031] According to a further aspect of the present invention, a lateralJFET includes a first semiconductor layer placed on a semiconductorsubstrate and containing impurities of a first conductivity type, asecond semiconductor layer placed on the first semiconductor layer andcontaining impurities of a second conductivity type with a higherimpurity concentration than that of the first semiconductor layer, athird semiconductor layer placed on the second semiconductor layer andcontaining impurities of the first conductivity type, a source regionlayer and a drain region layer spaced from each other by a predetermineddistance in the third semiconductor layer and containing impurities ofthe second conductivity type with a higher impurity concentration thanthat of the second semiconductor layer, and a gate region layer providedbetween the source region layer and the drain region layer in the thirdsemiconductor layer. The gate region layer, the second semiconductorlayer and the third semiconductor layer have respective thicknesses andrespective impurity concentrations that are determined to allow thethird semiconductor layer located between the gate region layer and thedrain region layer as well as a part of the second semiconductor layerthat is in contact with the third semiconductor layer all to be changedinto a depletion layer when a predetermined voltage is applied.

[0032] With this structure, the lateral JFET having a high withstandvoltage is easily achieved without increase in thickness of the secondsemiconductor layer and increase in resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a schematic diagram for illustrating operatingprinciples of a lateral JFET according to the present invention.

[0034]FIG. 2 is a cross sectional view showing a structure of a lateralJFET according to a first embodiment of the present invention.

[0035]FIG. 3 is a cross sectional view showing a structure of a lateralJFET according to a second embodiment of the present invention.

[0036]FIG. 4 is a cross sectional view showing a structure of a lateralJFET according to a third embodiment of the present invention.

[0037]FIG. 5 is a cross sectional view showing a structure of a lateralJFET according to a fourth embodiment of the present invention.

[0038]FIG. 6 is a cross sectional view showing a structure of a lateralJFET according to a fifth embodiment of the present invention.

[0039]FIG. 7 is a cross sectional view showing a structure of aconventional lateral JFET.

[0040]FIG. 8 schematically shows the conventional lateral JFET forevaluating the withstand voltage thereof.

[0041]FIG. 9 shows a relation between maximum voltage Vdgmax applicableto a region between the source and drain and the impurity concentrationof the channel.

[0042]FIG. 10 shows a relation between maximum current Vdgmax applicableto a region between the drain and gate and the impurity concentration ofthe channel layer.

BEST MODES FOR CARRYING OUT THE INVENTION

[0043] Embodiments of the present invention are now described inconjunction with the drawings. FIG. 1 is a schematic diagram forconceptually illustrating operating principles of the present invention.Although an electric field distribution between the gate and drainregions will be described with reference to FIG. 1, the same descriptionis applicable to an electric field distribution between the gate andsource regions. A lateral JFET according to the present invention has abasic structure including an n-type semiconductor layer 3 formed of ann-type impurity region and a p-type semiconductor layer 8 formed of ap-type impurity region on n-type semiconductor layer 3. Further, in thisp-type semiconductor layer 8, there are provided a p⁺-type gate regionlayer 7 extending into n-type semiconductor layer 3 and having a higherconcentration of p-type impurities than the impurity concentration ofn-type semiconductor layer 3 as well as an n⁺-type drain region layer 9placed with a predetermined distance from p⁺-type gate region layer 7and having a higher concentration of n-type impurities than the impurityconcentration of n-type semiconductor layer 3.

[0044] An electric field distribution between p⁺-type gate region layer7 and n⁺-type drain region layer 9 in this structure is hereinafterdescribed.

[0045] A Poisson equation for n-type semiconductor layer 3 isrepresented by following expression (5):

∂Ex/∂x+∂Ey/∂y+∂Ez/∂z=−ρ/ε  (5)

[0046] where

[0047] ρ represents a space charge density and ε represents a dielectricconstant.

[0048] As Ex is equal to 0 (Ex=0), expression (5) can be represented asexpression (6) below.

∂Ey/∂y=−ρ/ε−∂Ez/∂z   (6)

[0049] An external voltage is applied to this structure in y direction,however, the depletion layer extends not only in y direction but also inz direction and accordingly expression (7) is substantially satisfied.

∂Ez/∂z=−ρ/ε  (7)

[0050] Thus, a condition ∂Ey/∂y=0, namely Ey=constant is substantiallysatisfied. With the above-described structure, an electric fielddistribution is achieved that is a constant electric field similar tothat of parallel-plate capacitors, instead of the electric fielddistribution observed for the normal pn junction. Accordingly, adecreased ON resistance is achieved while the breakdown voltageperformance is maintained, as compared with the lateral JFET of theconventional structure. Embodiments are now described for a specificstructure of a lateral JFET employing the above-discussed structure.

[0051] First Embodiment

[0052] Referring to FIG. 2, a structure of a lateral JFET is describedaccording to this embodiment. The semiconductor substrate used here is asingle crystal SiC substrate of any conductivity type. On this singlecrystal SiC substrate 1, a p⁻-type epitaxial layer 2 which is a firstsemiconductor layer containing impurities of a first conductivity typeis provided as shown in FIG. 2. On this p-type epitaxial layer 2, ann-type epitaxial layer 3 is provided that is a second semiconductorlayer containing impurities of a second conductivity type with a higherconcentration than that of p⁻-type epitaxial layer 2. On this n-typeepitaxial layer 3, a p-type epitaxial layer 6 is provided that is athird semiconductor layer.

[0053] In this p-type epitaxial layer 6, an n⁺-type source region layer5 and an n⁺-type drain region layer 9 are provided at a predetermineddistance therebetween that contain impurities of the second conductivitytype with a higher concentration than the impurity concentration ofn-type epitaxial layer 3. Further, between source region layer 5 anddrain region layer 9, a p⁺-type gate region layer 7 is provided that hasits bottom surface extending into n-type epitaxial layer 3 and containsimpurities of the first conductivity type with a higher concentrationthan the impurity concentration of n-type epitaxial layer 3.

[0054] A source electrode 10, a gate electrode 11 and a drain electrode12 are provided respectively on respective surfaces of n⁺-type sourceregion layer 5, p⁺-type gate region layer 7 and n⁺-type drain regionlayer 9. A p⁺-type semiconductor layer 4 is provided on one lateral sideof source region layer 5.

[0055] It is supposed here that the lateral JFET with the structuredescribed above has a withstand voltage of 500 V, n-type epitaxial layer3 has a thickness of 1.0 μm, source region layer 5 and drain regionlayer 9 have a thickness (d) of 0.5 μm, p-type epitaxial layer 6 andn-type epitaxial layer 3 have the same impurity concentration of1.2×10¹⁷ cm⁻³, and p⁻-type epitaxial layer 2 has a thickness (h) of 3.0μm and an impurity concentration of 1.0×10¹⁶ cm⁻³. Then, “Lgd” is 2.2μm. For a normally-off type, “Lgs” is approximately equal to 0 and “a”is less than 160 nm (“a”<160 nm).

[0056] The structure of this embodiment provides an electric fielddistribution which is a constant electric field similar to that ofparallel-plate capacitors, instead of the electric field distribution ofthe normal pn junction. Accordingly, as compared with the lateral JFETof the conventional structure, a decreased ON resistance is achievedwhile the withstand voltage is maintained.

[0057] In addition, the impurity concentration of the secondsemiconductor layer is made equal to that of the p-type epitaxial layer6 to effectively decrease the ON resistance by the greatest degree whilethe withstand voltage is maintained.

[0058] Second Embodiment

[0059] Referring to FIG. 3, a structure of a lateral JFET according tothis embodiment is now described. The above-discussed lateral JFET ofthe first embodiment has p-type epitaxial layer 6 provided on n-typeepitaxial layer 3 and n⁺-type source region layer 5, n⁺-type drainregion layer 9 and p⁺-type gate region layer 7 are provided in thisp-type epitaxial layer 6. According to the second embodiment, thelateral JFET does not include p-type epitaxial layer 6 onn-type-epitaxial layer 3 and has its n⁺-type source region layer 5,n⁺-type drain region layer 9 and p⁺-type gate region layer 7 formed inn-type epitaxial layer 3. This structure is the same as that of thefirst embodiment except for the above-described details.

[0060] The structure as described above also provides an electric fielddistribution which is a constant electric field similar to that ofparallel-plate capacitors, instead of the electric field distribution ofthe normal pn junction. Accordingly, a decreased ON resistance isachieved while the withstand voltage is maintained, as compared with thelateral JFET of the conventional structure.

[0061] Moreover, distance (a) between the top of p⁻-type epitaxial layer2 and the bottom of p⁺-type gate region layer 7 is made smaller than thedistance of a depletion layer extended by a built-in potential at thejunction between n-type epitaxial layer 3 and p⁺-type gate region layer7. The depletion layer extended by the built-in potential causescomplete pinchoff of the channel when the gate is 0 V and thus thenormally OFF type is achieved.

[0062] Third Embodiment

[0063] Referring to FIG. 4, a structure of a lateral JFET according tothis embodiment is described. The lateral JFET of this embodiment hasthe same basic structure as that of the first embodiment, and onefeature of the third embodiment is that one impurity injection region 17is provided, in n-type epitaxial layer 3, between p⁻-type epitaxiallayer 2 and p⁺-type gate region layer 7, and this region 17 has almostthe same impurity concentration and the same potential as those ofp⁺-type gate region layer 7.

[0064] This structure also provides an electric field distribution whichis a constant electric field similar to that of parallel-platecapacitors, instead of the electric field distribution of the normal pnjunction. Accordingly, a decreased ON resistance is achieved while thewithstand voltage is maintained, as compared with the lateral JFET ofthe conventional structure.

[0065] Further, distance (a1) in this structure between the top ofimpurity injection region 17 and the bottom of p⁺-type gate region layer7 is made smaller than twice the distance of a depletion layer extendedby a built-in potential at the junction between n-type epitaxial layer 3and p⁺-type gate region layer 7, and distance (a2) between the bottom ofimpurity injection region 17 and the top of p⁻-type epitaxial layer 2 ismade smaller than the distance of a depletion layer extended by abuilt-in potential at the junction between n-type epitaxial layer 3 andimpurity injection region 17. Then, by the depletion layers extended bythe built-in potential, complete pinchoff of the channel occurs when thegate is 0 V and thus the normally OFF type is achieved.

[0066] Fourth Embodiment

[0067] Referring to FIG. 5, a structure of a lateral JFET according tothis embodiment is described. The lateral JFET of this embodiment hasthe same basic structure as that of the lateral JFET of theabove-discussed third embodiment, having a feature that a plurality ofimpurity injection regions 17 a and 17 b are provided, in n-typeepitaxial layer 3, between p⁻-type epitaxial layer 2 and p⁺-type gateregion layer 7, and the regions 17 a and 17 b have almost the sameimpurity concentration and the same potential as those of p⁺-type gateregion layer 7.

[0068] The structure as described above also provides an electric fielddistribution which is a constant electric field similar to that ofparallel-plate capacitors, instead of the electric field distribution ofthe normal pn junction. Accordingly, a decreased ON resistance isachieved while the withstand voltage is maintained, as compared with thelateral JFET of the conventional structure.

[0069] Moreover, for the structure as described above, distance (a1)between the top of impurity injection region 17 a that is closest top⁺-type gate region layer 7 among the impurity injection regions and thebottom of p⁺-type gate region layer 7 is made smaller than twice thedistance of a depletion layer extended by a built-in potential at thejunction between n-type epitaxial layer 3 and p⁺-type gate region layer7, distance (d) between impurity injection regions 17 a and 17 b is madesmaller than twice the distance of the depletion layer extended by thebuilt-in potential at the junction between n-type epitaxial layer 3 andp⁺-type gate region layer 7, and distance (a2) between the bottom ofimpurity injection region 17 b that is closest to p⁻-type epitaxiallayer 2 among the impurity injection regions and the top of p⁻-typeepitaxial layer 2 is made smaller than the distance of a depletion layerextended by a built-in potential at the junction between n-typeepitaxial layer 3 and impurity injection regions 17 a and 17 b. Thus, bythe depletion layer extended by the built-in potential, completepinchoff of the channel occurs when the gate is 0 V and accordingly thenormally-OFF type is achieved.

[0070] Fifth Embodiment

[0071] A structure of a lateral JFET according to this embodiment is nowdescribed. For respective structures of the above-discussed embodiments,decrease of the impurity concentration of n-type epitaxial layer 3 andincrease of the thickness thereof in the direction of the depth of thesubstrate are necessary for increasing the withstand voltage of thedevice. Then, a resultant problem is a sudden increase of the resistanceof n-type epitaxial layer 3. In addition, when the thickness of n-typeepitaxial layer 3 is increased in the direction of the depth of thesubstrate, a further problem of difficulty in control of the channelthickness occurs.

[0072] This embodiment is described below by being compared with thestructure of the first embodiment, with reference to FIG. 7. It is notedhere any component which is the same as that of the structure of thefirst embodiment is denoted by the same reference character and detaileddescription thereof is not repeated.

[0073] For the lateral JFET of this embodiment, in order to change intoa depletion layer, when a predetermined voltage is applied, all of ap-type epitaxial layer 6A between a p⁺-type gate region layer 7A andn⁺-type drain region layer 9 and a part of an n-type epitaxial layer 3Athat is in contact with this p-type epitaxial layer 6A, respectiveimpurity concentrations and respective thicknesses in the direction ofthe depth of the substrate of p⁺-type gate region layer 7A, n-typeepitaxial layer 3A and p-type epitaxial layer 6A are selected.

[0074] Specifically, according to this embodiment, p⁺-type gate regionlayer 7A includes, in the direction in which p⁺-type gate region layer7A extends (X direction of the substrate (see FIG. 1), a region 7Lprovided to reach p⁻-type epitaxial layer 2 and a region 7H provided toreach n-type epitaxial layer 3A.

[0075] Moreover, p-type epitaxial layer 6A has its impurityconcentration (ND) and thickness (dp) in the direction of the depth ofthe substrate, p⁺-type gate region layer 7A has its impurityconcentration (NA) and thickness (dn) in the direction of the depth ofthe substrate, and these concentrations and thicknesses are defined tohave the following relation. If the thicknesses have a relation dp=dn,the concentrations have a relation 2NA=ND. If the thicknesses have arelation 2dp=dn, the concentrations have a relation NA=ND.

[0076] The structure satisfying the relation above is employed to changeinto a depletion layer, when a predetermined voltage is applied, all ofthe p-type epitaxial layer 6A located between p⁺-type gate region layer7A and n⁺-type drain region layer 9 and a part of n-type epitaxial layer3A that is in contact with p-type epitaxial layer 6A. Accordingly,without increase in thickness of n-type epitaxial layer 3A and increasein resistance, a lateral JFET having a high withstand voltage isachieved.

[0077] While the embodiments of the present invention have beendescribed above, the embodiments disclosed above are by way ofillustration and example only and the scope of the present invention isnot limited to these embodiments, The scope of the present invention isset forth in the appended claims and it is intended that the sameincludes all of modifications and variations equivalent in the meaningand within the scope of the invention.

[0078] Industrial Applicability

[0079] According to the present invention, a lateral JFET is providedthat has a decreased ON resistance while maintaining a high breakdownvoltage-performance.

1. A lateral junction field-effect transistor comprising: a firstsemiconductor layer (2) placed on a semiconductor substrate (1) andcontaining impurities of a first conductivity type (p); a secondsemiconductor layer (3) placed on said first semiconductor layer (2) andcontaining impurities of a second conductivity type (n) with a higherimpurity concentration than that of said first semiconductor layer (2);a third semiconductor layer (6) placed on said second semiconductorlayer (3) and containing impurities of the first conductivity type (p);source/drain region layers (5, 9) spaced from each other by apredetermined distance in said third semiconductor layer (6) andcontaining impurities of the second conductivity type (n) with a higherimpurity concentration than that of said second semiconductor layer (3);and a gate region layer (7) provided between said source/drain regionlayers (5, 9) in said third semiconductor layer (6), having its bottomsurface extending into said second semiconductor layer (3) andcontaining impurities of the first conductivity type (p) with a higherimpurity concentration than that of said second semiconductor layer (3):2. The lateral junction field-effect transistor according to claim 1,wherein said second semiconductor layer (3) and said third semiconductorlayer (6) have substantially the same impurity concentration.
 3. Thelateral junction field-effect transistor according to claim 1, whereinthe distance between the top of said first semiconductor layer (2) andthe bottom of said gate region layer is smaller than the distance of adepletion layer extended by a built-in potential at junction betweensaid second semiconductor layer (3) and said gate region layer.
 4. Thelateral junction field-effect transistor according to claim 1, whereinan impurity injection region (17, 17 a, 17 b) is provided in said secondsemiconductor layer (3) between said first semiconductor layer (2) andsaid gate region layer (7), said impurity injection region havingsubstantially the same impurity concentration and the same potential asthose of said gate region layer (7).
 5. The lateral junctionfield-effect transistor according to claim 4, wherein one said impurityinjection region (17) is provided.
 6. The lateral junction field-effecttransistor according to claim 5, wherein the distance between the top ofsaid impurity injection region (17) and the bottom of said gate regionlayer (7) is smaller than twice the distance of a depletion layerextended by a built-in potential at junction between said secondsemiconductor layer (3) and said gate region layer (7), and the distancebetween the bottom of said impurity injection region (17) and the top ofsaid first semiconductor layer (2) is smaller than the distance of adepletion layer extended by a built-in potential at junction betweensaid second semiconductor layer (3) and said impurity injection region(17, 17 a, 17 b).
 7. The lateral junction field-effect transistoraccording to claim 4, wherein at least two said impurity injectionregions (17 a, 17 b) are provided.
 8. The lateral junction field-effecttransistor according to claim 7, wherein the distance between the top ofone (17 a) of said impurity injection regions that is closest to saidgate region layer (7) among said impurity injection regions and thebottom of said gate region layer (7) is smaller than twice the distanceof a depletion layer extended by a built-in potential at junctionbetween said second semiconductor layer (3) and said gate region layer(7), the distance between said impurity injection regions (17 a, 17 b)is smaller than twice the distance of the depletion layer extended bythe built-in potential at junction between said second semiconductorlayer (3) and said gate region layer (7), and the distance between thebottom of one (17 b) of said impurity injection regions that is closestto said first semiconductor layer (2) among said impurity injectionregions and the top of said first semiconductor layer (2) is smallerthan the distance of a depletion layer extended by a built-in potentialat junction between said second semiconductor layer (3) and saidimpurity injection region (17 b).
 9. The lateral junction field-effecttransistor according to claim 1, wherein said second semiconductor layer(3) and said third semiconductor layer (6) have substantially the samethickness, and said third semiconductor layer (6) has its impurityconcentration substantially half that of said second semiconductor layer(3).
 10. The lateral junction field-effect transistor according to claim1, wherein said third semiconductor layer (6) has its thicknesssubstantially half that of said second semiconductor layer, and saidthird semiconductor layer (6) and said second semiconductor layer (3)have substantially the same impurity concentration.
 11. A lateraljunction field-effect transistor comprising: a first semiconductor layer(2) placed on a semiconductor substrate (1) and containing impurities ofa first conductivity type (p); a second semiconductor layer (3) placedon said first semiconductor layer (2) and containing impurities of asecond conductivity type (n) with a higher impurity concentration thanthat of said first semiconductor layer (2); source/drain region layers(5, 9) spaced from each other by a predetermined distance in said secondsemiconductor layer (3) and containing impurities of the secondconductivity type (n) with a higher impurity concentration than that ofsaid second semiconductor layer (3); and a gate region layer (7)provided between said source/drain region layers (5, 9) in said secondsemiconductor layer (3) and containing impurities of the firstconductivity type (p) with a higher impurity concentration than that ofsaid second semiconductor layer (3).
 12. A lateral junction field-effecttransistor comprising: a first semiconductor layer (2) placed on asemiconductor substrate (1) and containing impurities of a firstconductivity type (p); a second semiconductor layer (3) placed on saidfirst semiconductor layer (2) and containing impurities of a secondconductivity type (n) with a higher impurity concentration than that ofsaid first semiconductor layer (2); a third semiconductor layer (6)placed on said second semiconductor layer (3) and containing impuritiesof the first conductivity-type (p); source/drain region layers (5, 9)spaced from each other by a predetermined distance in said thirdsemiconductor layer (6) and containing impurities of the secondconductivity type (n) with a higher impurity concentration than that ofsaid second semiconductor layer (3); and a gate region layer (7A)provided between said source/drain region layers (5, 9) in said thirdsemiconductor layer (6), including a region having its bottom surfaceextending to said first semiconductor layer (2) and a region having itsbottom surface extending to said second semiconductor layer (3), andcontaining impurities of the first conductivity type (p) with a higherimpurity concentration than that of said second semiconductor layer (3).13. A lateral junction field-effect transistor comprising: a firstsemiconductor layer (2) placed on a semiconductor substrate (1) andcontaining impurities of a first conductivity type (p); a secondsemiconductor layer (3) placed on said first semiconductor layer (2) andcontaining impurities of a second conductivity type (n) with a higherimpurity concentration than that of said first semiconductor layer (2);a third semiconductor layer (6) placed on said second semiconductorlayer (3) and containing impurities of the first conductivity type (p);a source region layer (5) and a drain region layer (9) spaced from eachother by a predetermined distance in said third semiconductor layer (6)and containing impurities of the second conductivity type (n) with ahigher impurity concentration than that of said second semiconductorlayer (3); and a gate region layer (7) provided between said sourceregion layer (5) and said drain region layer (9) in said thirdsemiconductor layer (6), wherein said gate region layer (7), said secondsemiconductor layer (3) and said third semiconductor layer (6) haverespective thicknesses and respective impurity concentrations that aredetermined to allow said third semiconductor layer (6) located betweensaid gate region layer (7) and said drain region layer (9) as well as apart of said second semiconductor layer (3) that is in contact with saidthird semiconductor layer (6) all to be changed into a depletion layerwhen a predetermined voltage is applied.